1. Field of the Invention
The present invention relates to a fabrication method of an active matrix type liquid crystal display having a thin film transistor as a switching element.
2. Description of the Related Art
A liquid crystal display has a feature to be light, a thin type and low power consumption, and is applied to a variety of areas such as a portable terminal, a finder of a video camera, a display of a notebook personal computer. Among them, an active matrix type liquid crystal display can display high quality and fine images, thereby being used for large displays for computers and the like. From now on, the more and more increase of the demands for the active matrix type liquid crystal display leads to the establishment of the fabrication method of the liquid crystal display having a high productivity at a low cost.
The conventional liquid crystal display and the fabrication method thereof are described with reference to FIG. 7 through FIG. 10. First, a schematic structure of the active matrix type liquid crystal display fabricated by the fabrication method of the conventional liquid crystal display is described with reference to FIG. 7. FIG. 7 shows a plan view of the substrate viewing an array substrate from the liquid crystal layer side. In FIG. 7, gate bus lines, the drain bus lines, and external connecting terminal areas of the bus lines for storage capacitors are shown along with the illustration of the pixel areas, omitting the intermediate illustration. As shown in FIG. 7, a plurality of drain bus lines 112 extending in the vertical direction in the diagram are formed on the array substrate. Further, on the array substrate, a plurality of gate bus lines 102 extending in the horizontal direction in orthogonal with the drain bus lines 112 in the diagram are formed. Areas decided by these drain bus lines 112 and gate bus lines 102 are pixel areas.
A sandwiching drain type TFT 100 is formed adjacent to the intersection position between the drain bus line 112 and the gate bus line 102 in each pixel area. A drain electrode 107 of the sandwiching drain type TFT 100 is pulled out from the drain bus line 112 and its edge is positioned on one edge side on an active semiconductor layer 104 (not shown in FIG. 7) on the gate bus line 102. At the same time, the end portion is formed crossing on the gate bus line 102 to prevent the signal mixing from the adjacent drain bus line. This drain electrode structure has a structure which sandwiches the area of the gate bus line 102 functioning as a gate electrode of the TFT 100 in the pixel area between the drain bus line 112 and the drain electrode 107. The active semiconductor layer 104 is formed above the gate bus line 102 and along the gate bus line 102 and ordinary is required to be electrically separated from the active semiconductor 104 of the TFT 100 in the other adjacent pixel area. However, according to such a sandwiching drain electrode structure, there is a merit that the patterning of the active semiconductor layer 104 for the TFT element separation between each pixel is not required and the number of the masks can be reduced in the photolithography process.
A source electrode 106 is formed on the other edge side on the active semiconductor layer 104 to oppose to the drain electrode 107. The source electrode 106 is electrically connected with a pixel electrode 114 formed along a shape of the pixel area. In the TFT structure shown in FIG. 7, the gate electrode is not formed by pulled out from the gate bus line 102. Therefore, the gate bus line 102 area arranged just under the active semiconductor layer 104 at the lower layer of source electrode 106 and the drain electrode 107 functions as the gate electrode 102 of the TFT 100. Although the illustration is omitted, a gate insulating film 103 is formed between the gate bus line 102 and the active semiconductor layer 104 thereon.
At the lower layer of the pixel electrode 114, a storage capacitor wiring 150 is formed in parallel with the gate bus line 102 and crosses substantially the center of the pixel electrode 114. A semiconductor layer (herein after referred to the active semiconductor layer 104 for convenience"" sake) is formed simultaneously with the active semiconductor layer 104 at the upper layer of the storage capacitor wiring 150. Therefore, it is required to electrically separate the semiconductor layer from the active semiconductor layer 104 on the storage capacitor wiring 150 in the other adjacent pixel area, and therefore a pixel separation area 162 is formed in an area between the drain bus line 112 and the pixel electrode 114 where the active semiconductor layer 104 is removed.
Further, an external connecting terminal 152 for an electrical connection with an external element is provided at one end portion of the drain bus line 112. Similarly, an external connecting terminal 154 for an electrical connection with an external element is provided at one end portion of the gate bus line 102 and an external connecting terminal 156 is formed at one end portion of the storage capacitor wiring 150. In FIG. 7, a short ring (a common electrode) 158 for an electrical connection between the external connecting terminal 154 of each gate bus line 102 is formed for an electrostatic protection in the fabrication process of the array substrate. Furthermore, a leading electrode 159 for the storage capacitor wirings is formed serving also as a common electrode. Although an illustration is omitted, a short ring electrically connecting each external connecting terminal 152 of the drain bus line 112 is separately formed. The short rings of these drain bus line and gate bus line, for example a short ring 158, are cut at the position of a dashed line 160 in FIG. 7 and separated after the array substrate and the opposing substrate are laminated.
Next, the conventional fabrication method of the liquid crystal display is described with reference to FIG. 8Aa through FIG. 10. FIG. 8Aa through FIG. 9Cc show partial cross sections showing the conventional fabrication process of the liquid crystal display. FIGS. 8Aa, 8Ab, 8Ac, 9Aa, 9Ab and 9Ac show cross sections adjacent to the TFT 100 cut at a line A-Axe2x80x2 in FIG. 7. FIGS. 8Ba, 8Bb, 8Bc, 9Ba, 9Bb and 9Bc show cross sections adjacent to the element separation area cut at a line B-Bxe2x80x2 in FIG. 7. FIGS. 8Ca, 8Cb, 8Cc, 9Ca, 9Cb and 9Cc show cross sections of the external connecting terminal 154 of the gate bus line 102 cut at a line C-Cxe2x80x2 in FIG. 7.
Now, as shown in FIGS. 8Aa, 8Ba and 8Ca, a metal thin film 164 depositing Al film and a Ti film thereon in this order is formed on a transparent insulating substrate (a transparent glass substrate) 110 of, for example, 0.7 mm in thickness as the array substrate by a sputtering method. Next, the gate insulating film 103 is formed by depositing for example a silicon nitride (SiN) film on the whole substrate surface by a plasma CVD method. Next, for example an amorphous silicon (a-Si) layer 166 for forming the active semiconductor layer 104 is deposited on the whole substrate surface by the plasma CVD method. Further, a n+a-Si layer 168 adding for example phosphorus (P) is formed on the whole substrate surface by the plasma CVD method to form a low resistance semiconductor layer 105 to be an ohmic contact layer.
Next, after resist is coated on the whole surface, the resist is patterned in a shape of the gate bus line and a shape of the storage capacitor wiring using a first resist exposure mask. The layers are etched together up to the metal thin film 164 using chlorine type gas by for example a reactive ion etching using the patterned resist layer (not shown) as a first etching mask, thereby as shown in FIGS. 8Ab, 8Bb and 8Cb areas for the gate bus line 102 and the external connecting terminal 154 of the gate bus line 102, and the leading electrode 159 of the storage capacitor wiring 150 and the external connecting terminal 156 (not shown) are formed along with the storage capacitor wiring 150.
Next, as shown in FIGS. 8Ac, 8Bc and 8Cc, after removing the resist layer, a sidewall insulating film 109 of the gate bus line 102 is formed. After coating for example organic polyimide on the whole substrate surface, this sidewall insulating film 109 is formed by performing an ashing treatment and the like until a surface of a low resistance semiconductor layer 168 exposes.
Next, as shown in FIGS. 9Aa, 9Ba and 9Ca, a metal film (not shown) is formed to form the drain electrode 107, the source electrode 106 and the drain bus line 112 by the sputtering method.
Next, a resist layer patterned in a shape of the source and drain electrodes and a shape of the data bus line is formed by coating a photo-resist on the whole substrate surface and by developing after exposing the resist using a second resist exposure mask. Using the patterned resist layer (not shown) as a second etching mask, the etching treatment is performed to the metal thin film, the n+a-Si layer 168 and a amorphous silicon layer 166 in this order. Then, as shown in FIGS. 9Aa, 9Ba and 9Ca, the drain bus line 112, the drain electrode 107, source electrode 106 and the low resistance semiconductor layer to be the ohmic contact layer are formed. In this etching treatment, one part of the upper part of the amorphous silicon layer 166 is also etched and the active semiconductor layer 104 is formed. In this etching, for example a reactive ion etching (RIE) is used and the chlorine type gas is used as an etching gas.
Further, as clear in FIGS. 9Aa, 9Ba and 9Ca, the amorphous silicon layer 166 for forming the gate insulating film 103 and the active semiconductor layer 104 remains at the upper portions of the gate bus line 102 and the external connecting terminal 154 and further at the upper portion of the storage capacity wiring 150 in this stage.
Next, the resist is again coated on the whole substrate surface after removing the resist layer. Then, the resist is developed after an exposure using a third resist exposure mask, thereby a resist layer is patterned in a shape of the element separation area and in a shape of the external connecting terminal. Using the patterned resist layer (not shown) as a third etching mask, the etching treatment is performed to the amorphous silicon layer 166 and the gate insulating film 103. As shown in FIGS. 9Ab, 9Bb and 9Cb, the element separation area 162 cutting the amorphous silicon layer 166 between the elements is formed. Further, the amorphous silicon layer 166 and the gate insulating film 103 on the external connecting terminal 154 are also removed by the etching and terminal surface thereof is exposed.
Next, after depositing a transparent electrode material, for example ITO (Indium Tin Oxide) layer on the whole surface, a photo-resist is coated on the whole substrate surface, developed after exposing the resist using a fourth resist exposure mask, and a resist layer is patterned in a shape of pixel electrode. Using this patterned resist layer (not shown) as a fourth etching mask, the pixel electrode 114 is formed as shown in FIGS. 9Ac, 9Bc and 9Cc by the etching treatment to the ITO layer. After the above processes, the array substrate forming the elements on the glass substrate is completed. A liquid crystal display panel is completed by laminating this array substrate and the opposing substrate after sandwiching liquid crystal.
The schematic fabrication process of the above conventional liquid crystal display is shown in FIG. 10. Steps (a) through (c) in FIG. 10 correspond to FIGS. 8 and steps (d) through (f) in FIG. 10 correspond to FIG. 9. In each process of steps (b), (d), (e) and (f) in FIG. 10, the resist exposure mask is required. In this example, since the TFT 100 has the sandwiching drain type structure, only two mask-processes are required to form the TFT 100. However, in the other processes, totally two masks for the resist exposure are required. One is for forming the etching mask to separate the active semiconductor layer on the storage capacitor wiring for each pixel and the other is for forming the etching mask for the pixel electrode 114. Four masks for the resist exposure are totally required in the whole array process.
Therefore, the depositing process for a predetermined film and the photolithography and etching processes composed of resist coating, resist baking, exposure, developing, etching, resist removing and the like are required for each of this four processes. Generally, such number of lithography processes is expressed by the number of masks and referred as a four-mask process in the above example. In the fabrication method of the liquid crystal display, generally, there is a problem that the more the number of masks used for the photolithography process increases, the more easily the damage due to an attachment of dust and the like occurs, thereby reducing a fabrication yield. Therefore, the number of the photolithography processes are desired to be as less as possible.
With a spread of the recent active matrix type liquid crystal display, more reduction of the fabrication cost is a very important subject to supply a liquid crystal display in the market at a low price and stably. In order to reduce the fabrication cost, first, it is strongly required to improve the fabrication yield of the liquid crystal display. Second, it is also required to increase a throughput in the fabrication of the liquid crystal display. For them, more high degree of depositing processes and the photolithography processes are required than the past along with the simplification of the fabrication processes. However, an introduction of the high performance fabrication equipment may on the contrary lead to an increase in cost. Further, with the current fabrication method, there is a limit to greatly improve the fabrication method and the throughput in front of the requirements for the finer and larger screen liquid crystal display. Further, comparing with the fabrication of the semiconductor equipment, the fabrication cost for masks used in the photolithography processes is higher in the fabrication of the liquid crystal display, thereby resulting in a problem in fabrication cost. However, there is a problem that in front of the requirement of the finer and larger screen of the liquid crystal display, above disadvantage must have been neglected.
An object of the present invention is to provide a fabrication method of a liquid crystal display which can reduce a fabrication cost.
Another object of the present invention is to provide a fabrication method of a liquid crystal display which can reduce the number of masks used in a photolithography process.
Above objects are achieved by a method of fabricating a liquid crystal display comprising which has features in laminating at least a gate forming metal layer, a gate insulating film, and an active semiconductor forming layer in this order on an insulating substrate, forming gate bus lines and storage capacitor wirings by etching the active semiconductor forming layer, the gate insulating film and the gate forming metal layer by using a first mask, forming a sidewall insulating film of each of the gate bus lines, depositing a transparent electrode material layer on the whole surface and then forming a first metal film thereon, forming drain bus lines, drain electrodes and pixel electrodes serving as source electrodes opposing to the drain electrodes by etching the first metal film and the transparent electrode material layer by using a second mask, forming a second metal film on the first metal film on the drain electrodes and forming a third metal film on the active semiconductor forming layer between the drain electrodes and the source electrodes and on the pixel electrodes by performing an electroplating, removing the active semiconductor forming layer on an element separation area between pixels by etching using the second metal film and the third metal film as a mask, and removing the third metal film.
According to the above structure of the present invention, it is possible to fabricate the array substrate of the liquid crystal display with two masks. After laminating the gate formation metal layer, the gate insulating film, the active semiconductor formation layer, and the low resistance semiconductor layer in this order, no mask is required to be used in the photolithography process other than the process for forming the gate electrodes and the storage capacitor wirings by etching together using the first mask and the process using the second mask for forming the source and drain electrodes. Instead, the present invention has a feature that the active semiconductor film is separated between the pixels and the pixel electrodes is formed using for example the plating and the selective etching.